Integrated circuit (IC) fabrication methods generally involve deposition of conductive metals into recessed features and other surfaces forming a layer of inter-layer dielectric (ILD). The deposited metal provides the conductive paths, which extend horizontally and vertically within the IC substrate, connecting the active devices (e.g., transistors) in a desired pattern. The metal lines formed in adjacent ILD layers are connected to each other by a series of interconnections (interconnects). On a typical wafer substrate, one or several dielectric layers are deposited onto a layer containing the active devices and are patterned to provide vertical and horizontal recessed features (vias and trenches), which are subsequently filled with conductive metals. The resulting layer containing metal-filled lines residing in a dielectric is referred to as a metallization layer. Copper is a commonly used metal in modern devices due to its low resistivity and high electromigration resistance. Aluminum is another frequently used metallization metal.
Some conductive metals, for example copper, can diffuse into the dielectric material that forms the trench or provides a surface and can impact dielectric properties. Maintaining low dielectric constants (low-k) is particularly important in ICs having densely packed features, where the insulating dielectric is thin and can lead to excessive capacitance. This can cause signal delay (RC time constant) and crosstalk between conducting lines, thus adversely affecting the performance of the device. A barrier is typically used to prevent conductive metals, particularly Cu, from diffusing into the dielectric. The diffusion barrier is a continuous layer deposited between the dielectric and the conducting metal and is usually sufficiently thick and made of materials that prevent migration of conductive metals from the line and via region. Many barrier materials are poor electronic conductors in comparison to copper and aluminum and also are resistive to initiating uniform and adherent electroplating thereupon. Hence these barriers typically require an additional conductive seed layer suitable to initiate and promote feature filling and electroplating of the conductive metal over the diffusion barrier layer. However, each such layer adds to production costs and complicates reducing the size of device nodes.
Further miniaturization of IC devices results in constantly decreasing dimensions of device features. Conductive line widths are already below 200 nm in many ICs, and it is expected that 40 nm lines will soon be commercially feasible. Electroplating copper or other material into such small features can present a set of challenges. Specifically, the diffusion barrier and conductive seed layers must be scaled down together with the line's dimensions. However, reducing thicknesses of these layers may lead to undesirable results. For example, barrier strength and conductance are directly dependent on the thicknesses of the corresponding layers. It may be desirable to eliminate one layer, such as a conductive seed layer, and electroplate directly onto a diffusion barrier layer that is sufficiently conductive. Moreover, many diffusion barrier materials do not adhere well to underlining dielectrics leading to poor Time Dependent Dielectric Breakdown (TDDB) behavior and Electromigration (EM) performance, both of which can cause premature failure of the IC, particularly in smaller circuit lines.
Overall, there is a need for improved diffusion barriers suitable for use within small dense features. Such barriers should be thin while providing good resistance to diffusion, conductivity, electromigration resistance, and adhesion-to-dielectric characteristics.